The present invention relates to multi-gate transistors and a method for fabricating the same, and more specifically, to multi-gate field effect transistors (FET) having plurality of sidewall contacts.
A typical complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) cell consists of several multi-gate FETs, for example, P-channel FETs and N-channel FETs. Each FET includes a metal gate stack and at least one semiconductor fin formed vertically along a substrate.
Today, the multi-gate FET has been a targeted structure for scaling CMOS technology to a sub 22 nanometer (nm) node, for example. Problems may include a short channel length and a short contact length in the gate pitch, thereby limiting the performance of the multi-gate FET and increases the FET's variability.